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application note, v1.0, oct. 2008 control integrated power system (cipos?) reference board for cipos tm ikcsxxf60b(2)x an-cipos-reference board-2 authors: junbae lee http://www.infineon.com/cipos power management & drives
edition 2008-10 published by infineon technologies korea seoul, south korea ? 2008 infineon technologies korea all rights reserved. legal disclaimer the information given in this application note is given as a hint for the implementation of the infineon technologies component only and shall not be regarded as any description or warranty of a certain functionality, condition or quality of the infineon technologies component. the recipi ent of this application note must verify any function described herein in the real application. infineon technologies hereby disclaims any and all warranties and liab ilities of any kind (including without limitation warranties of non-infringement of intellectual property rights of any third party) with respect to any and all in formation given in this application note. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies components may be used in life-support devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. for questions on technology, delivery and prices please contact the infineon technologies offices in germany or the infineon technologies companies and representatives worldwi de: see our web page at http://www.infineon.com . trenchstop ? , cipos tm , coolmos ? and coolset ? are a trademarks of infineon technologies ag. control integrated po wer system (cipos?) reference board for cipos tm ikcsxxf60b(2)x revision history: 2008-10 v1.0 previous version: page subjects (major chan ges since last version)
application note 3 v1.0, 2008-10 control integrated po wer system (cipos?) reference board for cipos tm ikcsxxf60b(2)x 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 external connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 signal connector (j1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 power connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 key parameter design guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1 circuit of input signals (lin , hin ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 bootstrap capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.3 short-circuit protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.3.1 shunt resistor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.3.2 delay time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.4 external fault-output duration time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.5 over-temperature protec tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5part list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 pcb design guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1 main consideration of layout design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.2 pcb design guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3 layout of reference board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
control integrated power system (cipos tm ) reference board for cipos tm ikcsxxf60b(2)x application note 4 v1.0, 2008-10 1 introduction this reference board is composed of the cipos tm ikcsxxf60b(2)x, its minimum peripheral components and sing le shunt resistor. it is design ed for customers to evaluate the performance of cipos tm with simple connection of the control signals and power wires. the electrical circuit of both refe rence boards for ikcsxxf60b(2)a and ikcsxxf60b(2)c is exactly same, however, pc b layout of them is different due to the difference of lead forming type betwee n ikcsxxf60b(2)a and ikcsxxf60b(2)c. figure 1 and figure 2 show the external view of two kinds of re ference boards. this application note descri bes how to design the key parameters and pcb layout. figure 1 reference board for cipos tm ikcsxxf60b(2)a figure 2 reference board for cipos tm ikcsxxf60b(2)c [ top ] [ bottom ] [ top ] [ bottom ]
control integrated power system (cipos tm ) reference board for cipos tm ikcsxxf60b(2)x application note 5 v1.0, 2008-10 figure 3 application example 1 2 3 4 56 78 910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 vcc vb1 \hin1 ho1 \hin2 vs1 \hin3 \lin1 vb2 \lin2 ho2 \lin3 vs2 \fault itrip vb3 en ho3 rcin vs3 vss com lo1 lo3 lo2 rts bridge diode cipos power connector power connector power connectors signal connector to controller cipos tm reference board ac smps controller filters & itrip, fo & temperature monitor circuits 3~
control integrated power system (cipos tm ) reference board for cipos tm ikcsxxf60b(2)x application note 6 v1.0, 2008-10 2 schematic figure 4 shows a circuitry of re ference board for cipos tm ikcsxxf60b(2)x. reference board consists of interface circuit, bootstr ap capacitors, sn ubber capacitor, short-circuit protection, over-t emperature protection, fault ou tput circuit and single shunt resistor. the cipos tm includes bypass capa citors of 100nf at ea ch vcc and vbs, so the external bypass capaci tors are not necessary. and the internal bypass capacitors are located very close to the drive ic, thus this is good advantage to prevent malfunction by noise. figure 4 circuit of reference board note : vctr denotes the controller supply voltage such as 5v or 3.3v for mcu or dsp. vb1 ho1 vs1 vb2 ho2 vs2 lo1 lo2 vb3 ho3 vs3 lo3 /hin1 /hin2 /hin3 /lin1 /lin2 /lin3 /fault rcin itrip en vss com vcc /hin1 /hin2 /hin3 /lin1 /lin2 /lin3 itrip vdd temp vss vb1 vb2 vb3 v+ u,vs1 v,vs2 w,vs3 vru vrv vrw 5 4 2 7 8 1 vctr (1) /uh (2) /vh (3) /wh (4) /ul (5) /vl (6) /wl (7) /fo (8) vsh (9) vntc (11) vdd (10) vctr (12) gnd p u v w n r1 r2 r3 r4 r5 r6 c1 c2 c3 c4 c5 c6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 c21 c7 r17 r23 r21 c16 r18 r19 c14 r20 c13 r22 c17 c18 c19 c12 c8 c9 c10 c11 j1 cipos tm ikcsxxf60b(2)x vctr vctr vctr vctr vctr vctr vctr 9 8 14 r24 r25 c20 vctr 11 10 13 r27 r28 c22 r26 vctr vctr c15 d5 q1
control integrated power system (cipos tm ) reference board for cipos tm ikcsxxf60b(2)x application note 7 v1.0, 2008-10 3 external connection 3.1 signal connector (j1) 3.2 power connector pin name description 1 /uh high side control si gnal input of u phase 2 /vh high side control signal input of v phase 3 /wh high side control si gnal input of w phase 4 /ul low side control signal input of u phase 5 /vl low side control signal input of v phase 6 /wl low side control signal input of w phase 7 /fo fault output signal 8 vsh shunt voltage sensing signal 9 vtemp temperature sensing signal of cipos tm 10 vctr external control voltage (5v or 3.3v) 11 vdd external 15v supply voltage 12 gnd ground pin description u output terminal of u-phase v output terminal of v-phase w output terminal of w-phase p positive terminal of dc-link voltage n negative terminal of dc-link voltage
control integrated power system (cipos tm ) reference board for cipos tm ikcsxxf60b(2)x application note 8 v1.0, 2008-10 4 key parameters design guide 4.1 circuit of input signals (lin , hin ) the input signals can be ei ther ttl- or cmos-compatible . the logic levels can go down to 3.3v. the maximum inpu t voltage of the pins is in ternally clamped to 10.5 v. however, the recommended voltage range of in put voltage is up to 5v. the control pins lin and hin are active low. they all have an inte rnal pull-up structure with a pull- up resistor value of nominal 75 k ? . the integrated pull-up resi stors are designed to pull up the internal structures, so that the ic can control cipos tm safely. for the more stable operation, an external pull- up circuit is necessary and re commended value is under 4.7k ? . the input noise filter inside cipos tm suppresses short pulse and prevents the driven igbt from excessive switching loss. the input noise filter time is typically 270ns. this means that an input signal must stay on its le vel for this period of time in order that the state change is pr ocessed correctly. and as shown in figure 5 , r of 100 ? and c of 1nf for the rc filter of interface circuit is recommended in orde r to operate safely in harsh environment in terms of emi. please place rc-filter as close to the input pins of cipos tm as possible. figure 5 rc-filter of input signals and pull-up circuit input noise filter vz=10.5v vcc 75k ? 50 ? /hinx /linx vctr rc filter controller (mcu or dsp) t filin =270ns cipos tm ikcsxxf60bx input noise filter vz=10.5v vcc 75k ? 50 ? /hinx /linx vctr rc filter controller (mcu or dsp) t filin =270ns cipos tm ikcsxxf60b2x vz=3.3v vcc 22k ? 22k ?
control integrated power system (cipos tm ) reference board for cipos tm ikcsxxf60b(2)x application note 9 v1.0, 2008-10 4.2 bootstrap capacitor bootstrapping is a common meth od of pumping charges from a low potential to a higher one. with this technique a supply voltage for the floating high side sections of the gate drive can be easily es tablished according to figure 6 . it is only the effective circuit shown for one of the th ree half bridges. the bootstrap resistor r bs is connected to each of the three bootstrap diodes in the module to limit current. please refer to the datasheet and application note for th e internal circuit and boot strapping method in detail. figure 6 bootstrap circuit for the s upply of a high si de gate drive a low leakage current of the high side sectio n is very important in order to keep the bootstrap capacitor s small. the c bs discharges mainly by th e following machanisms: - quiescent current to the hi gh side circuit in the ic - gate charge for turn ing high side igbt on - level-shift charge required by level shifters in the ic - leakage current in the bootstrap diode - c bs capacitor leakage current (ignored for non-electrol ytic capacitor) - bootstrap diode reve rse recovery charge the calculation of the boot strap capacitor results in with i leak being the maximum discharge current of c bs , t p the maximum on pulse width of high side igbt and ? v bs the voltage drop at the bootst rap capacitor within a switching period. practically, the reco mmended leakag e current is 1ma of i leak for cipos tm . vcc vss gate drive ic cipos tm r bs d bs v+ vb vs ho lo c dd c bs vbs c bs i leak t p ? v bs --------------------- - =
control integrated power system (cipos tm ) reference board for cipos tm ikcsxxf60b(2)x application note 10 v1.0, 2008-10 figure 7 shows the curve corresponding to abov e equation for a continuous sinusoidal modulation, if the voltage ripple ? v bs is 0.1v. the recommended bootstrap capacitance for a continuous sinusoidal modulation method is therefore in the range up to 4.7f for most switching frequencies. in other pwm method case like a discon tinuous sinusoidal modulation, tp must be set the longest period of the low side igbt off. figure 7 size of the bootstrap capacito r as a function of the switching frequency f pwm 4.3 short-circuit protection the reference board has a comp arator circuit for the short-circuit (sc) protection and fault output signal. the sc pr otection level is decided by reference voltage in negative input of comparator and comparator outp ut is connected to itrip pin of cipos tm . please refer to figure 8 for a detail circuit of sc protection. figure 8 short-circuit protection circuit 0 1 2 3 4 5 0 5 10 15 20 f pwm [khz] c bs [uf] 5 4 2 7 8 1 r14 r15 r16 c21 r17 r23 r21 c16 r18 r19 c14 r20 c13 c8 vctr vctr vctr vctr vctr 11 10 13 r27 r28 c22 r26 vctr vctr c15 q1 itrip vru vrv vrw vss cipos tm /fo v sc(ref) shunt resistor r13
control integrated power system (cipos tm ) reference board for cipos tm ikcsxxf60b(2)x application note 11 v1.0, 2008-10 4.3.1 shunt resistor selection the value of shunt resist or is calculated by the following equation. where v sc(ref) is the sc reference voltage of comparator negative input and i sc is the current of sc detection level. in the figure 8 , v sc(ref) is determined by voltage divi der(r27, r28). for example, when the control voltage vctr is 5v, r27=10k ? and r28=1k ? then v sc(ref) is 0.45v typ. . the sc reference voltage should be selected according to the application and user?s demand. the resistor for voltage divider shou ld be a precision resi stor such as 1% to decrease tolerance. the maximum value of sc protec tion level should be set le ss than the re petitive peak collector current in the da tasheet considering the tole rance of shunt resistor. for example, the maximum peak collector current of ikcs12 f60b(2)a is 18a peak , so the recommended value of shunt resistor is over 25m ? for ikcs12f60b(2)a. for the power rating of the shunt resistor , the below lists shou ld be considered. - maximum load current of inverter (i rms ) - shunt resistor va lue at tc=25c (r sh ) - power derating ratio of shunt resistor at t sh =100c - safety margin and the power rating is calculated by following equation. for example, in case of ikcs12f60b(2)a and r sh =25m ? - max. load current of inverter : 6a rms - power derating ratio of shunt resistor at t sh =100c : 80% - safety margin : 30% so the proper power rating of shunt resistor is over 2w. r sh v sc ref () i sc -------------------- - = r sh min () 0.45 18 ? 0.025 ? == p sh i rms 2 r sh min arg derating ratio ------------------------ -------------------------- - = p sh 6 2 0.025 1.3 0.8 --------------------- -------------------- - 1.46w ==
control integrated power system (cipos tm ) reference board for cipos tm ikcsxxf60b(2)x application note 12 v1.0, 2008-10 based on the prev ious equations, conditions, and calaulation method, minimum shunt resistance and resistor power ac cording to all kinds of cipos tm ikcsxxf60xxx products are introduced as shown in below table. it?s noted that a proper resi stance and its power over th an minimum values should be chosen considering over-current protection level required in the application set. products maximum peak current minimum shunt resistance, r sh minimum shunt resistor power, p sh ikcs22f60x(2)x 45 10m ? 4w ikcs17f60x(2)x 30 15m ? 3w ikcs12f60x(2)x 18 25m ? 2w ikcs08f60x(2)x 12 38m ? 1w
control integrated power system (cipos tm ) reference board for cipos tm ikcsxxf60b(2)x application note 13 v1.0, 2008-10 4.3.2 delay time the rc filter should be nece ssary in sc sensing circuit to prevent malfunction of sc protection due to noise interf erence. the rc time constant is determined by applying time of noise and the withst and time capability of igbt. when the current on shunt resistor exceeds sc protection level(i sc ), this voltage is applied to the positive input pi n of comparator via the rc filter. the f ilter delay time(t1) that the positive input voltage of comparator rises to the sc reference voltage is caused by rc filter time constant. in addition there are the respon se time of comparator(t2), inpu t filter time of itrip(t3) and shutdown propagation dela y of itrip(t4). please refer to the below table. therefore, the total delay time from occurr ence of sc to shutdown of the igbt gate becomes the total delay should be less than 5us of short circuit withstand time(t sc ) in datasheet. thus, rc time constant should be set in the range of 1~2us. it is recommended that r of 1.8k ? and c of 1nf. 4.4 external fault-output duration time if the itrip pin voltage of cipos tm exceeds the positive threshold voltage of itrip v it,th+ , then cipos tm turns off all 6-igbts during 4ms(t fltclr ). so the output of comparator(/fo) should be kept low over 4ms and the controller shou ld be off state a fter the fault signal is detected. an external fault-output duration time is over 5ms by rc time constant of r21 and c16, where the control supply voltage vctr is 5v or 3.3v, r21 is 510k ? and c16 is 10nf. it can be also cotrolled by changi ng the resistance and capacitance which are connected to the compar ator negative input. please refer to figure 8 for the circuit and figure 9 for the timing chart of sc protection. item min. typ.max.unit response time of comparator (t2) - 300 - ns input filter time of itrip (t3) 155 225 380 ns shutdown propagation delay (t4) - 900 - ns t total 2xt1 t2 t3 t4 +++ =
control integrated power system (cipos tm ) reference board for cipos tm ikcsxxf60b(2)x application note 14 v1.0, 2008-10 figure 9 timing chart of sc protection control input output current igbt gate voltage of shunt resistor negative input of comparator (pin #10) v sc(ref) v sc(ref) sc protection level (i sc ) fault-output signal (comparator pin #1) fault-output duration time (over 5ms)
control integrated power system (cipos tm ) reference board for cipos tm ikcsxxf60b(2)x application note 15 v1.0, 2008-10 4.5 over-temperature protection the cipos tm includes ntc of 100k ? at 25c. the ntc should be pulled up to 5v or 3.3v with external re sistor (r22), and v temp is determined by volt age divider (r24, r25). for example, when the control voltage vctr is 5v or 3.3v, r22=20k ? , r24=7.5k ? and r25=2k ? , then v temp at 100c of ntc te mperature is 1.06v typ. at vctr=5v and 0.7v at vctr=3.3v, and the set level of over-temperature protection at ntc is about 100c as shown in figure 10 and figure 11 . after over temperature protecti on is set, operating mechanism of this function is same as short-circuit protection like fault out and internal 6 igbts shut down. therefore, please refer to the chapter 4.3. figure 10 over-temperature protection with ntc figure 11 voltage of temp pin according to ntc temperature 5 4 2 7 8 1 r15 r16 c21 r17 r23 r21 c16 r18 r19 c14 r20 c13 c17 vctr vctr vctr vctr vctr 9 8 14 r24 r25 c20 r26 vctr vctr c15 q1 itrip temp vss cipos tm ikcsxxf60b(2)x /fo v temp(ref) r22 vctr rts d5 c23 0.0 1.0 2.0 3.0 4.0 5.0 0 20406080100120 ntc temp. [ ] v temp [v] ot set : 1.06v at vctr=5v ot set : 100 ot set : 0.7v at vctr=3.3v vctr = 5v vctr = 3.3v
control integrated power system (cipos tm ) reference board for cipos tm ikcsxxf60b(2)x application note 16 v1.0, 2008-10 5 part list symbol components note r1~r6 4.7k ? , 1/8w, 5% pull-up resistors for input signal r7~r12 100 ? , 1/8w, 5% series resi stors for input signal r13 5w, 5% current sensing resistor r14 1.8k ? , 1/8w, 5% series resistor for current sensing voltage r15 1k ? , 1/8w, 1% voltage devide r for reference voltage r16 3.9k ? , 1/8w, 1% voltage devide r for reference voltage r17 3.9k ? , 1/8w, 5% pull-up resistor for comparator output (v itrip ) r18 10k ? , 1/8w, 1% voltage devide r for reference voltage r19 20k ? , 1/8w, 1% voltage devide r for reference voltage r20 2k ? , 1/8w, 5% pull-up resistor for comparator output (fo ) r21 510k ? , 1/8w, 5% pull-up resistor for comparator input (fo ) r22 20k ? , 1/8w, 1% pull-up resistor for temperature sensing r23 1k ? , 1/8w, 5% base resistor of npn transistor r24 7.5k ? , 1/8w, 5% voltage devider for v temp r25 2k ? , 1/8w, 5% voltage devider for v temp r26 4.7k ? , 1/8w, 5% pull-up resistor for comparator output r27 10k ? , 1/8w, 5% voltage devider for v sc(ref) r28 1k ? , 1/8w, 5% voltage devider for v sc(ref) c1~c6 1nf 25v bypass capa citors for input signal c7 0.1uf 630v snubber capacitor c8 1nf 50v bypass capacitor fo r current sensing voltage c9~c11 4.7uf 35v bootstrap capacitors c12 100uf 16v +5v bias vo ltage source capacitor c13 100pf 25v bypass capacito r for fault-output signal c14,c15 100nf 25v bypass capaci tors for reference voltage c16 10nf 25v bypass capacitor for fo duration time c17 100nf 25v bypass capacitor for ntc temperature sensing c18 220uf 35v +15v bias vo ltage source capacitor c19 100nf 25v bypass capacitor for +5v c20 100nf 25v bypass capaci tor for reference voltage c21 1nf 25v bypass capacito r for comparator output
control integrated power system (cipos tm ) reference board for cipos tm ikcsxxf60b(2)x application note 17 v1.0, 2008-10 c22 100nf 25v bypass capaci tor for reference voltage c23 1000nf 25v bypass capacitor fo r signal stable of comparator output d5 1n4148 diode for bl ocking c23 voltage u1 cipos tm control intergra ted power system u2 lm2901n quad comparator for fault-output signal q1 2n2222 npn transistor j1 12pin connector signal & power supply connector u,v,w,p,n fasten ta ppower terminals
control integrated power system (cipos tm ) reference board for cipos tm ikcsxxf60b(2)x application note 18 v1.0, 2008-10 6 pcb design guide in general, there are several issues to be considered when designing a inverter board as below lists. - separate signal line and power line - low stray indu ctive connection - isolation distance - component placement this chapter explains above consideratio ns and method for the layout design. 6.1 main consideration of layout design figure 12 example of interface circuit note. 1. (1)~(4) patterns should be as short as possible. 2. signal gnd(2) and power gnd(4) s hould be connected at only one point. 3. all of the bypass capacitors shou ld be placed as close to the cipos tm as possible. 4. vs(5) and main output(6) patterns should be separated. 5. the snubber capacitor (c7) should be placed as close to the cipos tm as possible. vb1 ho1 vs1 vb2 ho2 vs2 lo1 lo2 vb3 ho3 vs3 lo3 /hin1 /hin2 /hin3 /lin1 /lin2 /lin3 /fault rcin itrip en vss com vcc /hin1 /hin2 /hin3 /lin1 /lin2 /lin3 itrip vdd temp vss vb1 vb2 vb3 v+ u,vs1 v,vs2 w,vs3 vru vrv vrw 5 4 2 7 8 1 vctr (1) /uh (2) /vh (3) /wh (4) /ul (5) /vl (6) /wl (7) /fo (8) vsh (9) vntc (11) vdd (10) vctr (12) gnd p u v w n r1 r2 r3 r4 r5 r6 c1 c2 c3 c4 c5 c6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 c21 c7 r17 r23 r21 c16 r18 r19 c14 r20 c13 r22 c17 c18 c19 c12 c8 c9 c10 c11 j1 cipos tm ikcsxxf60b(2)x vctr vctr vctr vctr vctr vctr vctr 9 8 14 r24 r25 c20 vctr 11 10 13 r27 r28 c22 r26 vctr vctr c15 d5 q1 (5) (6) (4) (4) (3) (2) (1)
control integrated power system (cipos tm ) reference board for cipos tm ikcsxxf60b(2)x application note 19 v1.0, 2008-10 6.2 pcb design guide figure 13 example of pcb layout note. 1. negative pin of bootstrap capacitor should be connected to output pin(u,v,w) directly and seperated from the ma in patterns of output. 2. the connection betwee n 3 emitters of cipos tm (vru,vrv,vrw) and shunt resistor should be as short and wide as possible to decrease stray inductance. 3. the capacitor for shunt voltage sensing sh ould be placed as close to comparator as possible. 4. in order to detect the sh unt voltage exactly, the sensing patter n of green and the ground pattern of blue should be wired from pin toward ce nter of shunt resistor, and stretched out as shown in figure 13 . 5. the snubber capaci tor should be placed as close to the te rminals as possible. 6. the power patterns of u,v, w,p and n should be designed on both layer with vias to cover the high current and th ere should be kept the is olation distance among the power patterns over 2.5mm. output dcp dcn vin vin +15v vctr gnd vru vrv vrw v+ vb1,vb2,vb3 /h in 1,/h in 2 ,/h in 3 /lin 1,/lin 2, /lin 3 itr ip vdd vss temp cipos tm 1 2 3 4 5 /fo u,v,w j1 6
control integrated power system (cipos tm ) reference board for cipos tm ikcsxxf60b(2)x application note 20 v1.0, 2008-10 6.3 layout of reference board figure 14 layout of reference board for cipos tm ikcsxxf60b(2)a [ top ] [ bottom ] 100mm 60mm [ top ] [ bottom ] 100mm 60mm
control integrated power system (cipos tm ) reference board for cipos tm ikcsxxf60b(2)x application note 21 v1.0, 2008-10 figure 15 layout of reference board for cipos tm ikcsxxf60b(2)c note. 1. all components except cipos tm ikcsxxf60b(2)c are placed on the top layer. 2. there are milling profiles in blue line to keep the isol ation distance between power patterns, where the isolatio n distance is not enough. [ top ] [ bottom ] 79mm 69mm [ top ] [ bottom ] 79mm 69mm
control integrated power system (cipos tm ) reference board for cipos tm ikcsxxf60b(2)x application note 22 v1.0, 2008-10 7 reference [1] infineon technologies: cipos tm IKCS12F60BA, ikcs12f60bc, ikcs08f60b2a; preliminary datasheet rev. 2; infineon technologies, germany, 2008. [2] infineon technologies: cipos tm ikcs12f60aa - reference board for cipos tm ikcs12f60aa; application note v 1.0; infineon technologies, korea, 2008

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